(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to split gate memory cells used in flash EPROMs (Electrically Erasable Programmable Read Only Memory).
(2) Description of Prior Art
Increased performance in computers is often directly related to a higher level of circuit integration. Tolerances play an important role in the ability to shrink dimensions on a chip. Self-alignment of components in a device serves to reduce tolerances and thus improve the packing density of chips. Other techniques can be important in shrinking device size. A method is disclosed later in the embodiments of the present invention of forming self-aligned source and drain regions through which a significant reduction in the split-gate flash memory cell area is possible. As is well known in the art, a split-gate flash memory cell normally has source and drain regions that are contacted by utilizing poly plugs. Insulating layers are required as spacers to separate these poly plugs from the floating gates and control gates of the cell, and this uses up area. Furthermore, because of the high voltages required in the erase operation the spacer width cannot be decreased without paying a penalty in reduced reliability. Elimination of the poly plugs, as in the method disclosed by the present invention, eliminates the reliability issue, allows a reduction in cell area and facilitates shrinking the cell size.
A method of fabricating a traditional split gate flash memory cell is presented in FIGS. 1a-1f, where top views of the cell are presented at successive stages of the process and in FIGS. 2a-2f, which show the corresponding cross-sections. Active regions, 10, are defined on a semiconductor substrate, 2, which preferably is a silicon substrate, using isolating regions, such as shallow trench isolation regions, 4. An implant is performed to adjust the cell threshold voltage, which may be a boron implant at about 20 keV to a dose of about 5E11 per sq. cm. The floating gate oxide, 6, is then formed to a thickness of about 150 Angstroms, followed by deposition of a poly 1 layer, 8, to a depth of about 800 Angstroms. A photoresist layer is formed and patterned to partially define the poly 1 floating gates, and after a poly 1 etch, to achieve the shape of region 8 as shown in FIG. 1a, and removal of the photoresist, the structure is as depicted in FIGS. 1a and 2a. The traditional method continues with formation of a dielectric separator between the poly 1 floating gate and poly 2 control gate that is disposed over the dielectric separator. This dielectric separator often consists of composite oxide/nitride/oxide (ONO) layers, with the layer thickness being about 75, 150, 30 Angstroms, respectively. There follows a deposition of about 1000 Angstroms of poly 2 and then about 1500 Angstroms of nitride 1. A photoresist layer is formed and patterned to define the control gates. Etching the nitride layer, the poly 2 layer and the ONO layer and then removing the photoresist results in the structure depicted in FIGS. 1b and 2b. The ONO layer, 54, provides dielectric separation between the poly 2 layer, 12, which acts as a control gate or transfer gate, and the poly 1 floating gate. The nitride 1 layer, 14, is required for dielectric separation between poly 2 and subsequent poly layers. A photoresist layer is formed and patterned, 18, to define source/drain openings, poly 1 is etched and source/drain implantation performed to create source/drain regions 16. Often arsenic ions are used for the source/drain implantation, at energy of about 50 keV to a dose of about 3E15 per sq. cm. After removal of the photoresist, 18, about 500 Angstrom of high temperature oxide (HTO) is formed and etched to create HTO spacers, 20. Next, about 1500 Angstroms of poly 3 is deposited and etched back to form poly plugs, 22, to contact the source drain regions, 16. The structure is at this stage as depicted in FIGS. 1d and 2d. Spacers 20 serve to isolate poly plugs, 22, from poly 1 regions, 8, and poly 2 regions, 12. For this isolation to be reliable the spacers must be sufficiently wide, posing a restriction on shrinkage of the cell. A photoresist layer is formed and patterned, 24, to define the erasing gate regions. Poly 3 and poly 1 of the exposed regions are etched. The structure of the floating gates 30 is now complete. An implant, often BF2 at about 60 keV to a dose of about 1E13 per sq. cm. , is performed to adjust the erasing gate threshold voltage and the exposed floating gate oxide, 6, is etched. At this point the structure is as depicted in FIGS. 1e and 2e. Following photoresist removal, about 250 Angstroms of erasing gate oxide, 26, is formed. Next the erasing gate, 28, is formed. This is accomplished by depositing about 1500 Angstroms of poly 4, forming and defining a photoresist layer for the erasing gate, etching the poly 4 and removing the photoresist. This completes the formation of a traditional split gate flash memory cell, which is shown in FIGS. 1f and 2f. 
There are three basic operations used in a split gate flash memory cell. These are the program operation, the erase operation and the read operation, which are shown in FIGS. 3a and 3b, FIGS. 4a and 4b, and FIGS. 5a and 5b, respectively. In the programming operation electrons are injected into a particular floating gate or bit, and the selection of the bit involves an erasing gate line acting as a word line and a drain line acting as a bit line. The programming process, the process of charging the floating gates, is shown in FIG. 3a. Voltages applied to control gate, 36, erasing gate, 28, and transfer gate, 36, form an n-channel. The voltage applied to the drain, 32, is sufficiently higher than that applied to the source, 34, so that channel electrons in the vicinity of the selected floating gate, 40, have been heated significantly. A higher voltage applied to the control gate, 36, causes an enhanced injection of the heated electrons into the floating gate, 40, which charges the floating gate. Selection of the programmed bit is illustrated in FIG. 3b. Successive erasing gate or word lines, 44, 28 and 46 have 0, 2 and 0 volts applied respectively. Only with cell 40 are the two necessary conditions for programming satisfied. It is along word line 28 with 2 volts applied, so a continuous channel is established between source and drain so that channel electrons can be heated by the source-drain potential difference. In addition, there is a higher voltage applied to its control gate to enhance injection of the heated channel electrons. Thus only bit 40 will be programmed. Other cells, 42, are not selected because either channel electrons are not heated, or there is no higher voltage applied to a control gate to facilitate electron injection into the corresponding floating gate or both conditions are absent. In the erase operation, shown in FIGS. 4a and 4b, a high voltage, sufficient to cause Fowler-Nordheim (F-N) tunneling through the poly-to-poly oxide between adjacent erasing and floating gates, is applied to an erasing gate word line, 28. All other voltages are maintained at 0 volts so that all floating gates along the biased word line, 40 in FIG. 4b, are selected, while cells 42, along unbiased word lines, such as 44 and 48, are not selected. The high erasing gate voltage required, achieving sufficient F-N tunneling, could present reliability issues due to high oxide stress. The read operation, in which the bit to be read is selected by a word line and a bit line, is shown in FIGS. 5a and 5b and determines if the selected bit is in the programmed state or in the erased state. With the source, 34, at 0 volts, 1.5 volts are applied to the drain line, 32, acting as the bit line, of the selected cell, 40, and 2 volts are applied to the erasing gate line, 28, acting as the word line of the selected cell, 40. There is 6 volts applied to transfer gates, 38 and 1.5 volts to control gates, 36. When the selected cell is in the programmed state a channel does not form under the selected cell and the drain current is low. On the other hand, when the selected cell is in the erased state a channel does form under the selected cell and there is thus a complete channel from source to drain and a large drain current is observed.
A method of forming polysilicon gate tips for enhanced F-N tunneling in split-gate flash memory cells is disclosed in U.S. Pat. No. 6,117,733 to Sung et al. A method for shrinking array dimensions of split-gate memory devices, using multilayer etching to define cell and source lines, is disclosed in U.S. Pat. No. 6,207,503 to Hsieh et al. In U.S. Pat. No. 6,204,126 to Hsieh et al. there is disclosed a split-gate flash memory cell where the floating gate of the cell is self aligned to isolation to source and to word line. In U.S. Pat. No. 6,228,695 to Hsieh et al. there is disclosed a split-gate flash memory cell where the floating gate of the cell is self aligned to the control gate and the source is self aligned.
It is a primary objective of the invention to provide a method of forming self-aligned source and drain regions through which a significant reduction in the split-gate flash memory cell area is possible. As is well known in the art, a split-gate flash memory cell normally has source and drain regions that are contacted by utilizing poly plugs. Insulating layers are required as spacers to separate these poly plugs from the floating gates and control gates of the cell, and this uses up area. Furthermore, because of the high voltages required in the erase operation the spacer width cannot be decreased without paying a penalty in reduced reliability. Elimination of the poly plugs, as in the method disclosed by the present invention, eliminates the reliability issue, allows a reduction in cell area and facilitates shrinking the cell size. Instead of poly plugs, a new self-aligned source/drain oxide etching procedure enables the formation of source/drain regions that are connected in rows directly within the silicon. This procedure of connecting source/drains is generally applicable to arrays of MOSFET-like devices.
A new structure is disclosed for source/drain bit lines in arrays of MOSFET devices. Rows of conducting regions are formed by ion implantation through openings adjacent to gate structures and in isolation regions separating columns of active areas of the arrays. The openings are filled with insulating material.